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<div class="textblock"><p>This header file contains layer 2 API's of the frame buffer read core driver.The functions contained herein provides a high level implementation of features provided by the IP, abstracting away the register level details from the user</p>
<p><b>Frame Buffer Read IP Features </b></p>
<p>The Frame Buffer Read IP supports following features</p>
<ul>
<li>AXI4-Stream Output</li>
<li>1, 2, or 4 pixel-wide video interface</li>
<li>8/10 bits per component</li>
<li>Up to 19 different memory color formats (user configurable)</li>
</ul>
<p><b>Dependency</b></p>
<p>This driver makes use of the video enumerations and data types defined in the Xilinx Video Common Driver (video_common_vX.x) and as such the common driver must be included as dependency to compile this driver</p>
<p><b>Initialization &amp; Configuration</b></p>
<p>The device driver enables higher layer software (e.g., an application) to communicate with the frame buffer read core.</p>
<p>Driver is built with layered architecture</p>
<ul>
<li>Layer 1 provides API's to peek/poke registers at HW level.</li>
<li>Layer 2 provides API's that abstract sub-core functionality, providing an easy to use feature interface</li>
</ul>
<p>Before using the layer-2 API's user must initialize the core by calling API <a class="el" href="group__v__frmbuf__rd.html#gaed42e419ae477b01e8677cabe9d07edc" title="This function initializes the core instance. ">XVFrmbufRd_Initialize()</a>. This function will look for a configuration structure for the device and initialize it to defined HW settings. It is recommended user always make use of Layer-2 API to interact with this core. Advanced users always have the capability to directly interact with the IP core using Layer-1 API's that perform low level register peek/poke.</p>
<p><b>Pre-Requisite's</b></p>
<ul>
<li>Application must set the memory address using provided API Address must be aligned to memory width. This can be computed with following equation Align = 2 * PPC * 4 Bytes (where PPC is the Pixels/Clock selected in IP configuration)</li>
<li>The Stride must be provided in Bytes and must be aligned to memory width. This can be computed with following equation StrideInBytes = 2 * PPC * 4 Bytes (where PPC is the Pixels/Clock selected in IP configuration)</li>
</ul>
<p><b> Interrupts </b></p>
<p>Driver is configured to operate both in polling as well as interrupt mode.</p>
<ul>
<li>To use interrupt based processing, application must set up the system's interrupt controller and connect the XVFrmbufRd_InterruptHandler function to service interrupts. Next interrupts must be enabled using the provided API. When an interrupt occurs, ISR will confirm if frame processing is is done/ready. If call back is registered such function will be called and application can apply new setting updates here. Subsequently next frame processing will be triggered with new settings.</li>
<li>To use polling method disable interrupts using the provided API. Doing so will configure the IP to keep processing frames without sw intervention.</li>
<li>Polling mode is the default configuration set during driver initialization</li>
</ul>
<p><b> Virtual Memory </b></p>
<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
<p><b> Threads </b></p>
<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
</p>
<hr/>
<p>
1.00  vyc   04/05/17   Initial Release
2.00  vyc   10/04/17   Add second buffer pointer for semi-planar formats
                       Add memory formats RGBA8, YUVA8, BGRA8, BGRX8, UYVY8
3.00  vyc   04/04/18   Add interlaced support
                       Add new memory format BGR8
                       Add interrupt handler for ap_ready
4.10  vv    02/05/19   Added new pixel formats with 12 and 16 bpc.
4.50  kp    13/07/21   Added new 3 planar video format Y_U_V8
4.60  kp    12/03/21   Added new 3 planar video format Y_U_V10
4.70  pg    05/23/23   Added new 3 planar video format Y_U_V8_420.
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